1. Field of the Invention
The present invention relates to a semiconductor packaging technology, and more particularly, to a ball grid array (BGA) package stack in which at least two BGA packages are stacked and interconnected.
2. Description of the Related Art
In the semiconductor industry, packaging technology for semiconductor integrated circuit (IC) chips has been continuously developed to satisfy market demands for a smaller package size, a greater pin count, and a higher mounting density on the motherboard. Additionally, with the development of high speed and high performance electronic devices, BGA type packages, which are in some respects superior in electrical and thermal properties to conventional lead-frame type packages, have grown in market share.
Stacking technology, which is a kind of packaging technology, is used to mount more packages on motherboards with limited size. Thus, stacking technology, including package and chip stacking, serves to increase the number of packages or chips per unit area of the motherboard. BGA packages have, however, certain difficulties in adopting the stacking technology because of structural limitations. A conventional stack structure of a BGA package is shown in FIG. 1.
Referring to FIG. 1, two individual BGA packages 11 and 12 are stacked and interconnected to form a BGA package stack 10. Stacking and interconnecting between the individual BGA packages 11 and 12 are made by solder balls 15. The solder balls 15 are formed under a circuit substrate 13 of an upper package 11 and joined onto a circuit substrate 14 of a lower package 12. Therefore, to effectively stack the BGA packages 11 and 12, the solder balls 15 should be located outside of a chip region 17. In other words, contrary to typical independent BGA packages, the BGA package 11 and 12 used for the conventional BGA stack 10 does not allow the solder balls 15 to be arranged evenly over a bottom surface thereof. As a result, the stacked BGA package becomes much greater in size than the chip due to the limits of ball arrangement. This makes the conventional BGA stack structure inapplicable to certain smaller type package such as certain chip size package (CSP). In addition, the solder ball 15 should have a large enough size to maintain a space between the upper and lower individual packages 11 and 12.